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Verilog course

Introduction to Verilog course objective
Introduction: Reasons for using the Hardware Language.
Hierarchical Design.
Types of Simulators, Compilation, and Synthesis.
Collapse Module
Structure of Basic Verilog Program.
Defining Module: Port list, Port modes.
Parameters
Instance Types: – Location
Collapse Data Types
Value Set.
Types of NET.
Strength.
ypes of REG: integer, real, time.
Parameters and Parameters Overriding.
Number Representation.
Collapse Data Flow
Continuous Assignments.
Implicit Continuous Assignment.
Collapse Procedural Blocks
Always in Synthesis Writing.
Always in Simulation Writing.
Initial: Structure and Example.
Intra Assignments.
Collapse Language Statements
If else
Case
Loop(while, repeat, forever, for)
Assign deassign
@, #, $
Collapse Lexical Conventions
Language Operators.
Concatenation and Replication.
Case Sensitivity.
Identifiers.
Escape Identifiers.
String.
Comments.
Strings.
Comments.
Collapse State Machines
Meally.
Moore.
One Hot.
Collapse Gate Level
Primitives in Verilog.
Vendor Libraries.
Display Messages.
Collapse Advanced Writing Simulation
Display Messages.
Managing files.
Memory Module.
Functions and tasks.
PLI- background.
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